A DFT architecture for asynchronous networks-on-chip

Abstract

The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC archi- tecture propositions are presented but few works on testing these network architectures. To test the SoCs, the main challenge is to reach into the embedded cores (ie, the IPs). In this case, the DFT tech- niques that integrate test architectures into the SoCs to ease the test of these SoCs are really favoured. In this paper, we present a new methodology for testing NoC architectures. A modular, generic, scalable and configurable DFT archi- tecture is ...